Micrologic

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Partners:

Jasper
Micrologic
AMIQ
Rosetta IP

Micrologic’s NanoToolBox accelerates signoff by enabling interactive, on-the-fly checks while performing custom layout using Cadence's Virtuoso or SpringSoft's Laker. This enables cutting the layout design cycle by as much as 50% and results in higher quality designs.

nanoDRC imports a signoff rule deck into the layout editor and enables automatic and continuous checks of the actual signoff rules during the layout phase. nanoDRC is currently used as deep as 28nm and supports all of the DRC rules, including complex conditional rules, connectivity rules, DFM rules, etc. It enables the user to use a single environment and minimizes the number of iterations between layout and signoff tools.

nanoRV enables checking reliability rules interactively, from the very early stages of the custom layout phase. It checks Electromigration, IR Filter, Self Heat, Fuse and Antenna Effects, taking into consideration the hot spots on the ASIC. nanoRV can read the outputs of Spice simulators (hSpice and Spectre) and use them in performing its analysis. It also incorporates sophisticated algorithms which enable it to provide important indications related to the reliability rules from very early in the design cycle, much before Spice results are available, significantly reducing the number of errors found and the number of issues waived when reaching signoff.

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